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GL Communications Announces Release of T1 E1 Hardware Product Feature Clock Slip Measurement

September 13, 2012

GL Communications (News - Alert), Inc. has introduced its latest T1 E1 Hardware product feature Clock Slip Measurement, which monitors Clock and Frame Slips on T1 E1 Lines.

“In a network, all switches use a single timing signal to transmit all signals in the outbound direction. This single timing is always derived directly from a single common reference timing signal available network-wide,” said said Jagdish Vadalia, senior manager of the company. “However, incoming signals may have timing variations due to propagation variations, re-clocking jitter, wander, frequency drift, etc. Due to this timing difference between transmit vs. receive signals; the network equipment may suffer an impairment by replicating data or deleting data. This is referred to as a timing, clock, bit or frame slip.”

Vadalia said clock slips are a count of the difference between a reference T1 E1 clock and another T1 E1 signal being measured. A clock slip is a one-second-interval measurement (accuracy of the timing slips is +/- 1 count) that arise because of phase differences or frequency differences of the incoming signal vs. the outgoing signal timing (the reference).

Enough clock slips (usually counts reaching 192 or 193) create a frame slip, and eventually, loses or repeats data.

GL’s T1 E1 Analyzer can measure clock slips between two T1 E1 timing signals, he elaborated. Different modes of clock slip that can be measured by T1 E1 hardware are-Internal Clock Slip Reference-This Clock Slip measurement compares the incoming receive clock from the port against the internal clock provided by the unit.

The software compares the internal counter to the recovered clock counter by storing these counts.

Crossport Clock Slip Reference-This Clock Slip measurement compares the incoming receive clock from Port #1 against the incoming receive clock from Port #2 using the Recovered Clock on Port #1 and Recovered Clock on Port #2.

“The other is External Clock Slip Reference, which compares the incoming receive clock using the recovered clock of Port 1 or 2 against the external clock provided on the external clock input,” said Vadalia. “In this case, the external clock must be either a T1 or E1 timing signal.”

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Edited by Braden Becker

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